The present invention relates to a method for fabricating an inverted staggered type thin film transistor with a high reliability using an amorphous silicon and a structure of the thin film transistor. More particularly, the present invention relates to a method for fabricating an inverted staggered type thin film transistor with a high reliability, which can prevent an undesired back channel effect, in which a channel is turned on during an off state of the thin film transistor to cause a leakage current, and relates to a structure of the thin film transistor. Further, the present invention relates to a method for fabricating a thin film transistor which can control a threshold voltage VFth of a front channel.
Thin film transistors (TFTs) using an amorphous silicon (a-Si) have been used in a large size image sensor or in a large size crystal display (LCD) since the TFTs can be formed on a large size substrate. A practical technology has been established for mounting a plurality of TFTs on a glass substrate as switching elements of picture elements (PELS) of a LCD.
The TFT is classified into a normally staggered type and an inverted staggered type depending upon the order of stacking various thin films on the substrate. In the normally staggered type TFT, a source electrode and a drain electrode are initially formed on the substrate, and a gate electrode is finally formed. In the inverted staggered type TFT, the gate is initially formed on the substrate, and the source electrode and the drain electrode are finally formed. The inverted staggered type TFT of these two types of TFTs has been frequently used in the LCD due to its easiness of fabrication and a stability of operational characteristics. In the inverted staggered type TFT, the gate electrode exists below a gate insulating film, and the source electrode and the drain electrode exist above the gate insulating film and are exposed to an external atmosphere, as shown in FIGS. 1C, 2D and 3D. Two fabrication methods of the inverted staggered type TFT are shown in the FIGS. 1A-1C and 2A-2D. FIGS. 1A-1C show the fabrication method of a channel etch type TFT 1, and the FIGS. 2A-2D show the fabrication method of a channel passivation type TFT 2.
In a Japanese Published Examined Patent Application 6-9246 and a Published Unexamined Patent Application 7-114285, for example, the fabrication method of the inverted staggered type TFT of the channel etch type is described as a prior technology. In a first step (a) shown in FIG. 1A, a structure is prepared in which, after a gate electrode 20 is patterned on a glass substrate 10, a gate insulating film 30, such as a silicon oxide film or a silicon nitride film, an amorphous silicon (a-Si) layer 40 of an order of a thickness of about 2000 xc3x85 and a n+a-Si film 70 as a low resistive film are sequentially stacked. In a step (b) shown in FIG. 1B, the patterns of the source and drain electrodes 80 is formed. Finally, in a step (c) shown in FIG. 1C, a portion of the n+a-Si layer 70 above a back channel region 100 of the a-Si layer 40 is removed by a reactive ion etching (RIE) process using the source and drain electrodes as a mask. During this etching, an upper interface of the a-Si layer 40 is partially removed. By using this fabrication method, the TFT array for the LCD in which a plurality of TFTs 1, as shown in the step (c), are formed is obtained.
However, a problem is caused in the fabrication method using the channel etching, that the channel region is damaged by an impact of the ions in the etching process. The impact of the ions in the etching process shown in FIG. 1C damages a front channel region 110 (an interface of the gate insulating film 30/the a-Si layer 40) and its electric characteristics, so that the stability of the TFT characteristics and a reliability of quality are degraded. To solve the damage to the front channel region 110 in the etching step (c), it can be considered to use the a-Si layer 40 of a thickness about 2000 xc3x85. However, this thickness of the a-Si layer 40 is four or five times of a thickness (xcx9c500 xc3x85) of an a-Si layer of a channel passivation film type TFT shown in the FIG. 2D, later described. Accordingly, a parasitic serial resistance having a value of several times of a contact resistance of the normal TFT exists between the source and the drain, so that a voltage normally applied to the PEL electrode can not provide a sufficient conduct characteristics during the turn on of the TFT. In the case that the channel etching type TFT 1 is used as the switching element of the LCD, a large size TFT is required to realize a sufficient write current. The use of the large size TFT in the PEL portion of the LCD causes an aperture ratio indicating a performance of the LCD to be decreased. The LCD panel comprises the area of PELs (the apertures through which the light passes) and the area of the other components. The aperture ratio is the ratio of the area of the PELS to the entire area of the LCD panel. The larger the aperture ratio is, the higher is the luminance of the display image of the LCD, so that a clear image is displayed and a large power saving effect is obtained. Usual LCD has the aperture ratio of 50-70%. In the case that the channel etching type TFT 1 is used as the switching element of the LCD, the large size TFT should be formed for each of the PELs to maintain a sufficient write current. As a result, the area of the TFT becomes large, so that the aperture ratio of the LCD panel using the TFTs is decreased.
In contradistinction to the TFT 1 fabricated by the channel etching process, the channel passivation film type TFT 2 shown in the FIG. 2D does not require the protection of the front channel region 110 from the damage applied in the etching process. The thickness of a-Si layer 40 of the usual channel passivation film type TFT 2 may be on the order of only about 500 xc3x85. The thickness of the a-Si layer of the channel passivation film type TFT 2 is sufficiently thinner than the thickness of the a-Si layer of the channel etching type TFT 1 shown in the FIG. 1C, the problem of decreasing the aperture ratio is solved in the structure of the channel passivation film type TFT 2. Describing the fabrication method of the channel passivation film type TFT 2, in step (a) shown in FIG. 2A, a structure is prepared in which, after the gate electrode 20 is patterned on the glass substrate 10, the gate insulating film 30, such as the silicon oxide film or the silicon nitride film, the a-Si layer 40 may have a thickness of about 500 xc3x85, and a silicon nitride film as a channel passivation layer 50 are sequentially stacked. In step (b) shown in FIG. 2B, the channel passivation layer 50 is patterned by using a resist mask pattern 60 formed above the gate electrode 20. In step (c) shown in FIG. 2C, the resist mask pattern 60 is removed, and a low resistive film 70 of the a-Si doped with the N type dopants is formed on the entire surface. In final step (d) shown in FIG. 2D, the patterns of the source and the drain electrode 80 are formed with respect to the gate electrode 20. A portion of the low resistive film (the n+a-Si) 70 above the back channel region 100 is etched by using the source and drain electrodes 80 as the mask, whereby the inverted staggered type TFT 2 in which the channel is protected by the passivation film is completed. In the Japanese Published Examined Patent Application 6-9246, one of the fabrication methods of the inverted staggered type TFT of the channel passivation film type is described.
In the channel passivation film type TFT 2 shown in the FIG. 2D, the channel passivation film 50 (for example the silicon nitride film) is continuously formed on the a-Si layer 40 in the step (a). When the a-Si layer 40 and the silicon nitride film 50 are continuously formed, the formation of lattice defects, to which the charges are putting in and out in an interface, between the a-Si layer 40 and the silicon nitride film 50 is suppressed. That is, a Density of States is small in an upper interface region (the back channel region) of the a-Si layer 40. In the case that the Density of States in the back channel region 100 is small, a consumption of a bias field for putting the electrons or the holes in and out the lattice defects is small in the back channel region 100. That is, in this structure, a leakage current tends to flow between the source electrode and the drain electrode by a small external electric field. Also, in the case that the Density of States is small, a scattering of the electrically conductive electrons and holes due to the lattice defects is also small. Accordingly, in the TFT2 in which the Density of States in the back channel region 100 is small, when the small back gate voltage 120 is applied to the turned off TFT, the leakage current flows between the source electrode and the drain electrode through the back channel region 100.
The case in the actual use of the LCD in which the back gate voltage 120 is generated at times during the off state of the TFT are, as follows. When impurity ions having the positive charges are placed on the TFT, or when the defects for generating the positive charges occur in the channel passivation film 50 of the TFT, the back gate voltage 120 is generated. Such phenomenon is called the back channel effects or the back gate effects in which, under the existence of such unexpected back gate voltage, an undesired and uncontrolled leakage current flows between the source electrode and the drain electrode through the back channel region 100 during the off state of the TFT. When the back channel effects occur during the off state of the TFT, the charges stored in a capacitor of each picture element of the LCD panel is discharged through the TFT, whereby the so called white strip occurs and the display quality is degraded.
As the method for preventing the back channel effects, the silicon oxide film has been used as the channel passivation film 50 in place of the silicon nitride film in step (a) shown in FIG. 2A. For example, the Japanese Published Unexamined Patent application 7-114285 discloses a method for fabricating the inverted staggered type TFT using the silicon oxide film as the channel passivation film. However, when the silicon oxide film is used as the channel passivation film 50, a mismatch between a lattice constant of the a-Si layer 40 and a lattice constant of the Sixe2x80x94O is large, whereby the defects tend to occur at the upper interface portion of the a-Si layer 40 even if the silicon oxide film is continuously formed on the a-Si layer 40. That is, the mismatch between the lattice constant of the a-Si layer and the lattice constant of the silicon oxide layer has an effect which causes the Density of States in the back channel region 100 to be large. However, since the capability for blocking ions which is required for channel passivation film 50 is low in the silicon oxide film, a new problem arises in that it passes impurity ions into the front channel region 110. Also, an etching rate of the silicon oxide film by a buffered hydrofluoric acid (HF) is very high, so that the control of the etching process in step (b) shown in FIG. 2B is difficult, resulting that the overhangs shown by dashed line in step (b) tend to occur. The channel lengths of the TFTs are widely scattered or varied by these overhangs. If the channel lengths of the TFTs used in the LCD are widely varied, the write operation is failed. Accordingly, in the case that the silicon oxide film is used as the channel passivation film 50, it is difficult to provide the TFTs with a reliable TFT characteristics and quality.
Accordingly, it has been required in the fabrication process of the channel passivation film type TFT shown in the FIG. 2D to suppress the back channel effects. Also, the fabrication process for realizing an easy control of the etching of the passivation film on the back channel region 100 of a-Si layer 40 in addition to the above requirement has been required to provide TFTs with reliable characteristics and quality.
It is one object of the present invention to provide a thin film transistor (TFT) and a fabrication method thereof which prevents the back channel effects in which the leakage current flows between the source electrode and the drain electrode during the off state of the TFT.
It is another object of the present invention to provide a fabrication method of the TFT for reducing the formation of the overhang in the channel passivation film on the a-Si layer in the etching process of the channel passivation film on the a-Si layer.
It is another object of the present invention to provide a fabrication method of the TFT which is capable of precisely controlling a threshold voltage VFth of the front channel and suppressing the back channel effects in which the leakage current flows due to the undesired turn on of the back channel during the off state of the TFT.
It is another object of the present invention to provide a fabrication method of the TFT which is capable of precisely controlling a threshold voltage VFth of the front channel.
The present invention forms a thin silicon oxynitride film having a thickness preferably equal to or less than 50 xc3x85 between a silicon layer and a channel passivation film above a back channel region between a source electrode and a drain electrode of an inverted staggered type TFT. The present invention prevents a leakage current due to the back channel effects to flow between the source electrode and the drain electrode by causing Sixe2x80x94O bonds to exist in an upper interface of the silicon layer to increase the Density of States in the back channel region. Since the thin silicon oxynitride film contains a large quantity of Sixe2x80x94N bonds, a small etching rate can be realized, whereby an easy control of the etching process can be obtained, resulting in the reliable inverted staggered type thin film transistor with a stabilized voltage-current characteristics.
A thin film transistor in accordance with the present invention includes a gate electrode, a gate insulating film, a silicon layer and source and drain electrodes formed on an insulating substrate in this order. A thin film transistor in accordance with the present invention includes a silicon oxynitride film formed on the silicon layer on a back channel region between the source electrode and the drain electrode, and a channel passivation film formed on the silicon oxynitride film.
A method for fabricating a thin film transistor in accordance with the present invention comprises the steps of: sequentially forming a gate insulating film, a silicon layer, a silicon oxynitride film and a channel passivation film in this order on an insulating substrate and a gate electrode formed on the insulating substrate; depositing a resist layer on the channel passivation film and forming a pattern of resist mask at a position above the gate electrode; etching portions of the channel passivation film and the silicon oxynitride film which are not covered by the resist mask; removing the resist mask; depositing a low resistive film on an entire surface of the structure; forming a source electrode and a drain electrode on the low resistive film at positions of both sides of the remaining channel passivation film; and removing a portion of the low resistive film which is placed on a back channel region between the source electrode and the drain electrode.
In the method for fabricating a thin film transistor in accordance with the present invention, a predetermined threshold voltage of a front channel can be realized by controlling a flow rate of N2 in a mixed gas containing SiH4, N2 and NO2 at the formation of the silicon oxynitride film by a chemical vapor deposition (CVD) method using the above mixed gas.